LXTALE from Intel Corporation. Find the PDF Datasheet, Specifications and Distributor Information. (This Datasheet also supports the LXT PHY.) Applications. Product Features LXTALE – Extended (° to 85 °C amb.) ▫ LXTALC. LXTALE Networking & Communications – Ethernet Products – Ethernet PHYs/ Macs/transceivers Details, datasheet, quote on part number: LXTALE.
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Each datasyeet identifies the highest common capabilities that both sides support and configures itself accordingly. This provides a very robust link, essentially filtering out any small noise datasheet that may otherwise disrupt the link. The speed is set automatically, once the operating conditions of the network link have been determined. It includes a state machine, data register array, and instruction register.
Device ID Register August 7, 43 LXTA 3. Current characterized errata are available on request. Added Table note 2. Before committing to a specific component, contact the manufacturer for current product specifications and validate the magnetics for the specific application.
A flip-flop and a latch are used for the serial shift stage and the parallel output stage. Status Register 2 Address 17 Bit The Lxt971xle registers are not accessible. For standard digital loopback testing Register bit 0.
SD input from the fiber transceiver. This signal is asynchronous and is inactive during fullduplex operation.
Intel products are not intended for use in medical, life saving, life sustaining applications. The hardware option uses the three LED driver pins.
LXTALE datasheet(39/90 Pages) INTEL | V Dual-Speed Fast Ethernet PHY Transceiver
Transmit Control Register Address 30 Bit BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. Test data sampled with respect to the rising edge of TCK. The BSDL file is available by contacting your local sales office or by accessing the Intel website www. Parallel detection allows the LXTA to communicate with devices that do not support auto-negotiation.
Default values of Register bits 4. Dual function input depending on the state of the device. The LXTA also supports additional registers for expanded functionality. The LXTA also provides two dedicated interrupt registers. August 7, 17 LXTA 3. Link failure causes the LXTA to re-negotiate if auto-negotiation is enabled. Loss of signal quality blocks any fiber data from being received and causes a link loss.
Unspecified or reserved combinations should not be transmitted. Refer to the Hardware Configuration Settings section on page 30 for additional details. Integrated, programmable LED drivers. Voltages with respect to ground unless otherwise specified. This feature is provided as a diagnostic tool.
Exposure to maximum rating conditions for extended periods may affect device reliability. To enable this function, set Register bit Center-tap current may be supplied from 3. However, RXD outputs zeros until the received data is decoded and available for transfer to the controller.
August 7, 75 LXTA 3. Its operating condition can be set using auto-negotiation, parallel detection, or manual control. Test Loopback is enabled when 0. This provides three control bits, as listed in Table 9.
Refer to Figure 3 on page 13 for specific pin assignments. This document also supports the LXT device.
Lx971ale 10 Mbps operation, Manchester-encoded data is exchanged. Typical values are for design aid only; not guaranteed and not subject to production testing.
Interrupt logic is shown in Figure 6. This output remains High for the duration of the collision. The default setting of Register bit 4. Figure 26 shows a typical example of an LXTA-to-5 V fiber transceiver interface, while Figure 27 shows the interface circuitry for the logic translator.
When the Link Integrity Test function is enabled the normal configurationit monitors the connection for link pulses.
August 7, 35 LXTA 3. Five seed bits are determined by the PHY address, and the remaining bits are hard coded in the design. Each channel has its own clock, data bus, and control signals.