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Using a bit latch would only add to your delay. Hi burnmeister, Can you give a few more details, why is the speed important, what sort of ADC etc.

In that case – and assuming you can solve the synchronization problem between DRDY and the ‘ instruction cycle – there are just enough instruction cycles to work. Perhaps the third set of comments will only triple the confusion – I hope it doesn’t cause the confusion to be cubed! The on-chip filtering combined with a high oversampling ratio ratio reduces the external antialias requirements.

I can’t be sure to catch the impuls cause it’s only during for ns. When i’m looking for the high period of DRDY with some code like this: This is clearly unusable. This architecture of oversample-then-decimate-in-the-data-domain bs1s25 to be fairly common. Remember that if you use Pic16F7x families. Thanks for the answers till now anyway!!

You already listed the fastest way to read two ports: It should take only a few seconds to tell if the 33uSec rise time is correct or not. Why does my PIC32 run slower than expected?


BSS124, BSS125, BSS129

I’m surprised by your statement: Embedded Software and Hardware Development User Control Panel Log out. If this is true, it is clearly unusable in your application.

I hope the circuit will run next monday. This includes the rise time of the signal source photodiode array plus the rise time of any anti-aliasing network on the analog input.

So I need only x2 Bytes to read in, but this has to pass very quick. Do you know the English word “stumped”? If you have same good ideas, please go on The AD is sampling continuously.

PIC16F Read the 16Bit of PortB&D at same time | Microchip

Depending on what you can control, I would suggest code like the following all timing statements assume Look at the data and see how fast the samples rise to the final value. From “Circuit Description” in the Data Sheet: Another problem can occur if there is no synchronisation between the two devices.

For your 16 MHz clock, this calculates to almost 34 uSec!! The analog rise time of whatever limits the input bandwidth. One Thing I still don’t understand: Writing an email to an analog devices engineer is also a good idea i will do next week!


Then i can monitor the ad-results in a fast way and make some experiments like you said! It was invented, as the Data Sheet says, to put us grey-haired analog filter designers out of work.

From the “General Description” section of the Data Sheet, “The analog input is continuously sampledeliminating the need for an external sample-and-hold. Allow me to add my comments to the dwtasheet. If I understand the question from “burnmeister” correctly, it can be re-stated as: Haven’t received registration validation E-mail?

So I can catch both of the bytes high and low in a time of approx ns: I think you should be more concerned about the other more prominant delays like the ADC conversion and acquisition, time taken to perform calculations on the data or to display it Gixy Super Member Total Posts: There must be a fatasheet time too or am I wrong?

BSS (Siemens) – Sipmos Small-signal Transistor (n Channel Enhancement Mode) | eet

The modulator output is processed by a finite impulse response FIR digital filter. The fastest pin-sampling loop I can think of is: I am not certain that timing diagram Figure 7b is correct for your application. My understanding of the diagrams is this: I’m using this 1.